The present invention relates to image processing systems and methods, and more particularly to digital systems and methods for processing grayscale images.
A wide variety of image processing systems have been developed enabling digital computers to "see" or "read" an image. Typically, these image processors include a video camera, an analog-to-digital converter for digitizing the video signal produced by the camera, and a digital system for processing the digitized information. For example, the image can be digitized into a matrix, or lattice, of pixels with each of 512 video scan lines divided into 512 pixels. In a nongrayscale, or binary, image, each pixel can be encoded in a single bit, which is set to zero if the pixel is dark and set to one if the pixel is illuminated. In a grayscale image, each pixel is encoded in a multibit word which is set to a value corresponding to the illumination intensity of the pixel. Grayscale images are more realistic and detailed than nongrayscale images. The image processors scan the digital images and process the digital information to interpret the image.
One extremely efficient nongrayscale image processor is disclosed in U.S. patent application Ser. No. 559,438, filed Dec. 8, 1983, by Sternberg et al., now U.S. Pat. No. 4,665,551, entitled APPARATUS AND METHOD FOR IMPLEMENTING TRANSFORMATIONS IN DIGITAL IMAGE PROCESSING (hereinafter "the Sternberg binary processor"). This processor includes digital circuitry for effecting dilations and other transformations of serialized bit-wide streams representative of nongrayscale images. More specifically, the processor includes a plurality of sequentially coupled logic units, each including a delay unit for delaying the serialized stream and a function unit for performing any one of a plurality of logical operations on the delayed and undelayed streams on a bit-by-bit basis. However, the Sternberg binary processor is capable of processing only bit-wide, or binary, data streams.
One extremely efficient grayscale image processor is disclosed in U.S. patent application Ser. No. 644,101, filed August 24, 1984, by Sternberg, now U.S. Pat. No. 4,641,356, entitled APPARATUS AND METHOD FOR IMPLEMENTING DILATION AND EROSION TRANSFORMATIONS IN GRAYSCALE IMAGE PROCESSING (hereinafter "the early Sternberg grayscale processor"). This processor includes digital circuitry for effecting dilations and erosions of serialized multibit wide streams representative of grayscale images. More specifically, the processor includes one or more sequentially coupled logic units, each including a delay unit for delaying the serialized streams, an adder for adding a constant value to each word in the delayed stream, and a comparator unit for selecting the larger of the delayed and undelayed streams on a word-by-word basis.
In further development of the early Sternberg grayscale processor, it has been recognized that the processor has two limitations. First, the operation of the logic units is not bounded. Consequently, manipulations of grayscale images occasionally produce data which exceeds the range of the processor's multibit format, producing virtual images which are difficult or even impossible to interpret. Second, the function unit is capable of selecting only a maximum value on a word-by-word basis between the delayed and undelayed streams. Consequently, the processor is capable of only dilation and erosion. The early Sternberg grayscale processor is therefore incapable of effecting many desired image transformations.
Another image processor, less efficient than the previously described Sternberg processors, routes a grayscale serial signal sequentially through several neighborhood transformations to detect limited image features. Disclosures of this processor are provided in U.S. Pat. No. 4,395,699, issued July 26, 1983, to Sternberg, entitled METHOD AND APPARATUS FOR PATTERN RECOGNITION AND DETECTION, and U.S. Pat. No. 4,322,716, issued Mar. 30, 1982, to Sternberg, entitled METHOD AND APPARATUS FOR PATTERN RECOGNITION AND DETECTION. At each neighborhood transformation stage, the "neighborhood" of pixels surrounding a given pixel in one image is examined and the corresponding pixel in the new image is given a value which is a function of the neighborhood pixels in the old image. All neighborhood pixels in an image are made available for processing by serially routing the digital image through one or more fixed-length shift registers. As the image is shifted through the registers, the appropriate register locations are simultaneously accessed to process a particular neighborhood. This neighborhood processor has drawbacks. First, the entire neighborhood of a pixel must be made available and examined before the corresponding pixel in the new image can be given a value. This requires excessively complicated circuitry to make the neighborhood pixels simultaneously available to drive the neighborhood function generator. Second, the neighborhood processing theory is an inefficient and cumbersome method of effecting many image transformations. Third, the neighborhood theory greatly restricts the operations which can be performed, due to the limited size or extent of the neighborhood.